卷积码编码及其Viterbi译码算法的FPGA实现

FPGA Implementation of Convolutional Code Encoding and Viterbi Decoding Algorithm

摘要:

探讨了卷积码编码及其Viterbi译码算法的FPGA（Field-Programmable GateArray）实现,根据编码器的结构,分别采用了有限状态机转换的编码法和基于流水线结构的状态转换译码法,有效地提高了编译码的速度.最后给出了（2,1,2）卷积码的编码及其Viterbi译码算法的实验仿真结果。

Abstract:

FPGA Implementation of Convolutional Code encoding and Viterbi Decoding Algorithm is presented.According to the structure of convolutional code,the conversion method of encoding based on limited state machines,and state conversion method of Viterbi Decodi