一种快速的二维中值滤波算法及其硬件实现

Implementation of Fast 2-D Median Filter on FPGA

摘要:

为了实现实时图像预处理，介绍了中值滤波器的原理，详细研究了一种快速的二维中值滤波算法，给出了Verilog程序流程，并在现场可编程门阵列（FPGA）上用硬件编程语言实现了此中值滤波器。通过对不同算法的仿真结果进行了详细分析和比较，表明此算法大幅度降低了FPGA的资源占用率，能有效控制系统成本，适合用于硬件实现。

Abstract:

The elements of median filter are introduced,then a fast 2-D median filter algorithm and its implementation are described.Comparing the fast algorithm and the regular one,the former requires much less resource of the FPGA.So its implementation can reduce