一种基于FPGA节省资源实现FIR滤波器的设计方法

A method of resources saving to realize FIR filter based on FPGA

摘要:

有限长脉冲响应(FIR)滤波器的结构决定了用现场可编程门阵列(FPGA)设计非常消耗触发器资源或存储器资源。以n阶滤波器为例，提出一种节省触发器和双口RAM的读写操作方法。通信系统应用仿真表明，与常规FIR滤波相比较，本文方法不仅滤波效果良好，而且大量减少乘法器和加法器数量，有效节省触发器和双口RAM。滤波器阶数越高，越节省资源。

Abstract:

The structure of FIR filter determines that it will consume a great deal of the resources of flip-flop or memory to design the FIR(Finite Impulse Response) filter by using the FPGA(Field Programmable Gate Array). Taking the n-order filters for example, a method of read and write operations to save the resources of flip-flop and dual-port RAM was presented. Comparing with a conventional FIR filter, the application simulation in a communication system showed that the method was not only good for filtering, but also in reducing a number of adders and multipliers, saving flip-flop and dual-port RAM effectively. The higher orders of filter, the more resources were saved.