一种I2C总线控制器的接口设计

An interface design for I2C bus master

摘要:

为了实现片上系统芯片与外围设备之间的通信，介绍一种从外围总线(APB)到I2C总线的接口设计。对整个系统按照功能进行了模块划分，阐述了APB总线接口的设计和寄存器配置、I2C总线控制器中的状态划分和状态机设计以及时钟产生模块的实现。设计中采用了异步先进先出来同步APB总线和I2C总线之间的数据交换。对整个设计进行了功能仿真，实现了系统在100 kbps和400 kbps两种工作模式下的数据传输。设计完全满足通信的速率要求。

Abstract:

In order to implement communication between System On Chip(SOC) and peripheral device，an interface design for data transfer between Advanced Peripheral Bus(APB) and Inter-Integrated Circuit(I2C) has been proposed in this article. It first describes the function partition of the whole system. Then the APB interface design and register configuration are introduced. The design of main state-machine of I2C bus and the implementation of clock generator are presented. Asynchronous First In First Out(FIFO) is adopted to synchronize data transfer between APB bus and I2C bus. Finally，the functional simulation has shown that the design performs well in both 100 kbps and 400 kbps. It completely meets the requirement for transfer speed.