一种自偏置锁相环结构的分析

Analysis of a self-offset Phase Lock Loop

摘要:

介绍了一种自偏置结构形式的锁相环设计方法，在一定程度上可以对锁相频率源输出信号质量进行改善，提升产品性能，简化设计。在没有增加额外环外混频频率信号的情况下，对改进后的锁相环电路进行测试，其相位噪声指标提高约10 dB，具有较大的工程应用优势。

Abstract:

Phase Lock Loop(PLL) frequency source is improved rapidly. This paper provides a design of a self-offset PLL. Based on the analysis and experimental verification for this design, it is indicated that the output signal quality of the PLL frequency source can be improved, and the design is simplified. The phase noise of the proposed PLL frequency source can be improved by 10 dB without additional mixing frequency signal. This proposed design shows great advantages in engineering practices.