基于晶振倍频鉴相的C波段低相噪频率源设计

Design of a C-band low phase noise frequency synthesizer based on phase detecting with crystal oscillator multiplication

摘要:

针对数字锁相技术相位噪声的构成和特性进行了探讨与研究，并在对比传统单环锁相方案的基础上，介绍了一种基于晶振倍频信号作为参考进行鉴相的低相噪频率合成器。经测试，传统锁相方案在输出6 480 MHz时，相位噪声为 。而本文设计的低相噪频率源在使用同样的参考晶振、锁相环芯片以及压控振荡器的情况下，输出相同频率时，相位噪声相比传统方案改善了约8 dB。

Abstract:

The phase noise composition and characteristics of a digital Phase Locked Loop(PLL) are investigated. A phase locked frequency synthesizer based on crystal oscillator multiplication is presented. Compared with the traditional frequency synthesizer based on single PLL，the proposed design achieves lower phase noise. According to the test results，the phase noise of -109.1 dB/Hz@10 kHz is achieved by the traditional approach when the output is 6 480 MHz; while a better phase noise performance of -117 dB/Hz@ 10 kHz is reached by the proposed design at the same frequency，using the same crystal oscillator PLL chip and Voltage Controlled Oscillato(VCO), which is improved by 8 dB compared to the traditional design.