一种真有效值测量方案设计与验证

Design and verification of a true root mean square measurement scheme

摘要:

针对目前国内真有效值(RMS)测量芯片依赖进口的问题，提出了一种基于现场可编程门阵列(FPGA)的数字式高精确度的真有效值测量方案。首先利用FPGA设计有限长单位冲击响应滤波器(FIR)对AD采样后的数据进行滤波，然后采用改进的有效值计算式计算信号的真有效值，最后取连续8个周期真有效值的平均值作为最终的测量结果。通过设计串行的开方运算、除法运算的算法，降低FPGA的使用资源。经过样机实际测试表明，测量结果与信号真值的相对误差低于0.5%。该方案测量精确度高，一致性好，使用资源少，对于真有效值数字测量芯片的设计和真有效值测量具有一定的参考价值。

Abstract:

A high-precision and digital true root mean square measurement method based on Field Programmable Gate Array(FPGA) is presented. Firstly, FPGA is employed to design Finite Impulse Response(FIR) filter to filter the AD sampled data. Furthermore, the improved RMS formula is adopted to calculate the true RMS of the signal. The mean value of the true RMS value of eight consecutive cycles is taken as the final measurement result. By designing the algorithms of serial extraction and division operations, the use of FPGA resources is reduced. The actual test of the prototype shows that the relative error between the measurement results and the true value of the signal is less than 0.5%. The solution has high measurement accuracy, good consistency, and less resources, which has certain reference value for the design of the true RMS digital measurement chip.