一种高速数字上变频的优化设计与实现方法

An optimal design and implementation method of high speed digital up conversion

摘要:

软件定义无线电(SDR)要求数模转换器采样率越来越高、发射信号的带宽越来越宽，传统的数字上变频方法受限于现场可编程门阵列(FPGA)的时钟频率，无法满足应用需求。提出一种优化的高速数字上变频(DUC)设计方法，对插值滤波及数字频率合成进行改进。推导出高速数字上变频的数学模型，对传统数字上变频结构进行优化；设计高效灵活的内插滤波实现结构和数字频率的合成结构；分析给出内插滤波器多路滤波系数和多路并行数字频率合成的相位参数计算方法。硬件实现表明，该优化设计方法功能正确，便于工程应用，输出的数字中频信号数据率可达960 MS/s。该方法可实现不同倍数的内插，产生不同速率的高速本振信号，能够满足软件无线电中发射大带宽、高速率信号的数字上变频应用需求。

Abstract:

The Software Defined Radio(SDR) requires that the Digital to Analog Converter(DAC) must have higher and higher sampling rate, and the bandwidth of the transmitted signal is wider and wider. The traditional method of the Digital Up Conversion(DUC) cannot meet the application requirements because of the limited clock frequency of the Field Programmable Gate Array(FPGA). An optimized design method of high speed DUC is proposed to improve interpolation filtering and digital frequency synthesis. Firstly, the mathematical model of high speed DUC is deduced and the traditional DUC structure is optimized and improved. The implementation structure of the efficient and flexible interpolation filtering, as well as the structure of the multichannel parallel digital frequency synthesis are designed. Secondly, the coefficients of interpolation filters are given as well as the computing method of phase parameters for parallel digital frequency synthesis. The hardware implementation shows that the function of the optimized method is correct , and the method is convenient for engineering application. The data rate of the output digital Intermediate Frequency(IF)signal can reach 960 MS/s. The optimized method can realize the interpolation of different multiples, and can also produce high speed Local Oscillator(LO) signals with different rates. It can meet the requirements of DUC applications which need to transmit wide band and high rate signals in SDR.