基于 RISC-V 架构的行人定位SoC系统设计

Design of pedestrian positioning SoC based on RISC-V architecture

摘要:

行人定位方法中，捷联式惯导定位系统需要处理惯性测量单元(IMU)传感器的数据，通过算法处理后得到行人的位置，因此对于芯片实时性以及低功耗有很高的要求。由于行人定位算法大多基于浮点传感器数据开发，一般要求终端设备能够处理浮点数据。第五代精简指令集(RISC-V)架构作为一种开源架构，能节约架构授权费，在物联网领域有着广泛应用，并且其浮点(F)和向量(V)等高性能扩展指令能够很好地满足行人定位算法对实时性的要求。针对行人定位系统的特定性能要求，提出了一种基于浮点内核向量处理器优化RISC-V架构的行人定位片上系统(SoC)，并在实际系统中进行验证。与多个准32位架构RISC-V处理器以及高层次综合组件(HLS)生成的算法专用IP(locate_IP)的标准处理器方案的性能对比分析表明，该设计实现了34倍的性能提升以及5.6倍的能效提升，满足了微终端的要求。

Abstract:

In pedestrian positioning methods, the strapdown inertial navigation system requires processing data from the Inertial Measurement Unit(IMU) sensors, and the position of the pedestrian is obtained after algorithmic processing, thus placing high demands on the real-time performance and low power consumption of the chip. Since most pedestrian positioning algorithms are developed based on floating-point sensor data, the terminal device is generally required to handle floating-point data. The fifth-generation Reduced Instruction Set Computer(RISC-V) architecture, as an open-source architecture, can save on architectural licensing fees and has a wide range of applications in the field of the Internet of Things. Moreover, its floating-point(F) and vector(V) high-performance extension instructions can well meet the real-time requirements of pedestrian positioning algorithms. In response to the specific performance requirements of the pedestrian positioning system, a System on Chip (SoC) for pedestrian positioning based on a floating-point core vector processor optimized RISC-V architecture is proposed and verified in actual systems. A performance comparison analysis with several quasi-32-bit architecture RISC-V processors and standard processor schemes of algorithm-specific IPs (locate_IP) generated by High-Level Synthesis(HLS) components shows that the design has achieved a 34-fold improvement in performance and a 5.6-fold improvement in energy efficiency, meeting the requirements of micro terminals.