基于InP基HEMT器件的D波段倍频源设计

Design of a D-band frequency multiplier source on InP-based HEMT

摘要:

传统太赫兹倍频源多采用混合集成电路的实现方式，导致太赫兹倍频源存在体积大、封装损耗高、稳定性差等问题。采用栅长2×25 μm的磷化铟(InP)基高电子迁移率晶体管(HEMT)有源器件，利用先进系统设计(ADS)原理仿真和电磁仿真(EM)联合仿真分析的方法设计了一款全单片集成的D波段倍频源。该倍频源采用倍频＋放大的形式设计实现，其中第一级为二倍频电路，第二级采用放大电路。在132~154 GHz范围内，当输入功率为4.5 dBm时，输出功率大于6 dBm，基波抑制比优于31 dBc，三次谐波抑制比优于36 dBc，最大输出功率为9 dBm@144 GHz，对应的变频增益为4.5 dB，该倍频源的芯片面积约为3.1 mm×1.3 mm。该设计为全单片集成的太赫兹源和实现小型化太赫兹源提供了新的选项。

Abstract:

Traditional terahertz frequency doublers often utilize hybrid integrated circuits as implementation methods, leading to issues such as large size, high packaging loss, and poor stability. By employing an active device based on indium phosphide(InP) High Electron Mobility Transistors(HEMT) with a gate length of 2×25 μm, a fully monolithic integrated D-band frequency doubler is designed by using a combined simulation analysis method of Advanced Design System(ADS) and electromagnetic(EM) simulation. The frequency doubler is designed in the form of frequency doubling plus amplification, with the first stage being a frequency doubling circuit and the second stage using an amplification circuit. Within the range of 132~154 GHz, when the input power is 4.5 dBm, the output power is greater than 6 dBm, the fundamental wave suppression ratio is better than 31 dBc, the third harmonic suppression ratio is better than 36 dBc, and the maximum output power is 9 dBm@144 GHz, with a corresponding frequency conversion gain of 4.5 dB. The chip area of this frequency doubler is approximately 3.1 mm×1.3 mm. This design provides a new option for fully monolithic integrated terahertz sources and the realization of miniaturized terahertz sources.