一种基于链式FIFO的雷达目标检测FPGA实现方法

A FPGA target detection of millimeter wave radar based on improved chain FIFO structure

摘要:

现有毫米波雷达目标检测主要基于串行处理平台实现，对大尺寸雷达图像处理的速度存在一定瓶颈。本文基于现场可编程门阵列(FPGA)提出一种以链式先进先出(FIFO)缓冲器为核心，融合图像提取思路的毫米波雷达目标快速检测结构。通过链式FIFO实现多帧数据对齐与并行输出，得到窗口边缘数据；根据自定义窗参数，将边缘数据分区求和并延时缓存，可实现对窗移动前后计算结果的复用，配合流水线式处理结构提高运算效率；对相邻子图像重叠区域合理划分，从大尺寸图像中提取出多个小尺寸子图像单独处理，大幅提升雷达目标检测算法的实现速度，并显著节省片上逻辑资源。基于92~94 GHz的调频连续波(FMCW)毫米波雷达对本文目标检测FPGA实现方法进行验证，对于1 000×2 000的大尺寸雷达图像可实现120 ms的快速处理，且FPGA布署算法仅消耗32个18K BRAM和6 461个LUT。

Abstract:

Existing millimeter-wave radar target detection is mainly implemented based on serial processing platforms, which have certain limitations in processing speed for large-sized radar images. This paper proposes a fast millimeter-wave radar target detection structure based on a Field-Programmable Gate Array(FPGA), with a chain-type First-In-First-Out(FIFO) buffer at its core and incorporating an image extraction approach. The chain-type FIFO enables multi-frame data alignment and parallel output to obtain window edge data. Based on custom window parameters, the edge data are partitioned and summed, and then delayed and cached. This allows for the reuse of computational results before and after window movement, and in combination with a pipelined processing structure, it improves computational efficiency. By reasonably partitioning the overlapping regions of adjacent sub-images and extracting multiple small-sized sub-images from large-sized images for separate processing, the implementation speed of the radar target detection algorithm is significantly increased, and on-chip logic resources are substantially conserved. The proposed FPGA-based target detection method is validated using a Frequency-Modulated Continuous Wave(FMCW) millimeter-wave radar operating in the 92~ 94 GHz band. For a large-sized radar image of 1,000×2,000 pixels, a rapid processing time of 120 ms is achieved. The deployed FPGA algorithm consumes only thirty-two 18K BRAMs and 6 461 LUTs.