Improve SRAM SEU resistance with SOI CMOS technology

Abstract:

Improving Single Event Upset(SEU) resistance of Static Random Access Memory(SRAM) is being a hotspot in the research area of electronics Radiation-Hardening. It is hard to improve the anti-SEU ability of bulk CMOS SRAMs without circuit Radiation-Hardening，whereas more area and power consumption will be spent with Radiation-Harding design. To investigate the SEU resistance of Silicon on Insulator(SOI) SRAMs，this study introduced the key technology breakthrough in SOI CMOS Radiation- Hardening process and 128 kb SRAM circuit design. The SEU experiment of a homemade 128 kb SOI SRAM showed that its threshold Linear Energy Transfer(LET) value was more than 61.8 MeV/(mg/cm2)，which was higher than that of CMOS SRAMs without Radiation-Hardening design. It is concluded that SOI fabrication process is promising to obtain preferable SEU resistance of SRAMs with proper considerations on basic device and 6-T cell structure.