Abstract:The design proposal and result of a FPGA-based Turbo decoder is introduced. Using the Max-Log-MAP decoding algorithm and the Verilog language for programming, the positive sequence operation and the reverse order operation can be simultaneously carried, and the intermediate results can be stored in array-based memory，which has enabled the decoding speed to be improved. The Turbo decoding theory, the Max-Log-MAP algorithmic analysis, the block diagram based on FPGA design and implementation, algorithm timing diagram and velocity analysis, are also presented. Results indicates that the program is correct and feasible, decoding/error correction is unmistakable, and the decoding speed is quick.