Abstract:The structure of FIR filter determines that it will consume a great deal of the resources of flip-flop or memory to design the FIR(Finite Impulse Response) filter by using the FPGA(Field Programmable Gate Array). Taking the n-order filters for example, a method of read and write operations to save the resources of flip-flop and dual-port RAM was presented. Comparing with a conventional FIR filter, the application simulation in a communication system showed that the method was not only good for filtering, but also in reducing a number of adders and multipliers, saving flip-flop and dual-port RAM effectively. The higher orders of filter, the more resources were saved.