An interface design for I2C bus master

Abstract:

In order to implement communication between System On Chip(SOC) and peripheral device，an interface design for data transfer between Advanced Peripheral Bus(APB) and Inter-Integrated Circuit(I2C) has been proposed in this article. It first describes the function partition of the whole system. Then the APB interface design and register configuration are introduced. The design of main state-machine of I2C bus and the implementation of clock generator are presented. Asynchronous First In First Out(FIFO) is adopted to synchronize data transfer between APB bus and I2C bus. Finally，the functional simulation has shown that the design performs well in both 100 kbps and 400 kbps. It completely meets the requirement for transfer speed.