A real-time PAPR reduction algorithm based on FPGA

Abstract:

Multi-carrier transmission has been employed widely for communications and jamming system. But high Peak to Average Power Ratio(PAPR) of the transmitted signal is a major drawback of multi-carrier transmission system. This paper introduces the definition of PAPR and some main methods of PAPR reduction. In order to reduce the large computation complexity of traditional methods and keep the invariability of spectrum，a real-time PAPR reduction algorithm based on Field Programmable Gate Array(FPGA) has been proposed. This method improves the traditional phasing algorithm and has been implemented in Virtex-5 chip of XILINX. The experiment results show that the proposed method can reduce the PAPR with low complexity，and thus is of good practicability.