Abstract:To enhance the operation speed and utilize the resource，according to the idea of hardware parallel method，one traditional implementation of genetic algorithms is improved by separating controlling part into other components and using Field Programmable Gate Array(FPGA) to realize control in pipelining mode. The result of synthesis shows its frequency can reach 137.08 MHz for evolution of a generation needing 64 cycles(namely 0.467 μs). With optimized hardware resources and high efficiency, the realized structure demonstrates the possibility of large-scale and high-speed hardware realization of genetic algorithms.