Design of a C-band low phase noise frequency synthesizer based on phase detecting with crystal oscillator multiplication

Abstract:

The phase noise composition and characteristics of a digital Phase Locked Loop(PLL) are investigated. A phase locked frequency synthesizer based on crystal oscillator multiplication is presented. Compared with the traditional frequency synthesizer based on single PLL，the proposed design achieves lower phase noise. According to the test results，the phase noise of -109.1 dB/Hz@10 kHz is achieved by the traditional approach when the output is 6 480 MHz; while a better phase noise performance of -117 dB/Hz@ 10 kHz is reached by the proposed design at the same frequency，using the same crystal oscillator PLL chip and Voltage Controlled Oscillato(VCO), which is improved by 8 dB compared to the traditional design.